Foundry workbench

NANDCORE

A working 64–32–10 binary neural net in NAND and LATCH. TapeOut cells take the dense XNOR array. Behemoth cells take the popcount trees and weight RAM.

Transistors
137.1k
Clock
12 MHz
Power
1017.8 µW
Asset
draft

Probe station

8×8 optical pad

64-bit vector

Argmax

Class latches

—

  1. 0
  2. 1
  3. 2
  4. 3
  5. 4
  6. 5
  7. 6
  8. 7
  9. 8
  10. 9

Draw a digit or load a glyph, then run the pipeline. Scores are 2·feature XNOR + template XNOR (max 128).

Hybrid die

TapeOut × Behemoth floorplan

TapeOut Behemoth
NANDCORE · 64–32–10 · XNOR / popcount / WTAI/O pad latches64 LATCHXNOR synaptic array12.7k NANDXNOR hot lanes2.3k NANDWeight SRAM1.9k LATCHWeight overflow1.1k LATCHPopcount CSA trees7.7k NANDPopcount spill5.0k NANDHidden latches32 LATCHArgmax / WTA160 NAND · 14 LATCHPipeline FSM116 NAND · 24 LATCH

Dense XNOR synapses sit in TapeOut NAND. Wide popcount trees and weight RAM use Behemoth cells at 6× drive so the critical path stays inside one clock at 12 MHz.

Clocked pipeline

Idle

cycle 0

  1. LOAD
  2. XNOR
  3. POP
  4. THR
  5. H32
  6. CLS
  7. WTA

Seven stages from pad latch through winner-take-all. Step or run the clock.

Traveler / BOM

Hybrid allocation

TapeOut denseBehemoth drive 62%
TapeOut NAND
17.8k
TapeOut LATCH
1.2k
Behemoth NAND
10.2k
Behemoth LATCH
1.9k
Transistors
137.1k
Energy
84.8 pJ
Delay
10.4 ns
Power
1017.8 µW

Gate probe

Neuron 8 · col0≥3

pop 5 / thr 3 · 1

5-NAND XNOR slice · mask bits only · TapeOut fabric(0,0)x wNANDXNOR(0,1)x wNANDXNOR(0,2)x wNANDXNOR(0,3)x wNANDXNOR(0,4)x wNANDXNOR(0,5)x wNANDXNOR(0,6)x wNANDXNOR(0,7)x wNANDXNOR

Each shown cell is a 5-NAND XNOR against a weight-1 mask bit. The Behemoth popcount tree sums all 8 hits and the threshold latch writes hidden[8].

Use case

MeterScan · always-on register OCR

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Utility meters, elevator floors, and kiosk PINs are four bright glyphs on a dark field. A 64–32–10 binary net built only from NAND and LATCH classifies each cell at microwatts, and the same netlist can be re-simulated bit-for-bit — the inference is the circuit.

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